High bit rate digital signals are degraded by frequency dependent losses in the signal path, including losses resulting from inter-symbol interference (ISI). Such losses are anticipated and are otherwise normal effects, and must be considered in the design of high bit rate serial transmitters and receivers. For example, an ISI loss filter may be designed to enable a user to apply expected signal path losses to a signal transmitted to a digital receiver, emulating existing or anticipated hardware. The output of the digital receiver may then be checked to determine whether it correctly recovered the digital data, regardless of the applied losses.
A viable ISI filter must operate over a wide frequency range, compensate for internal losses associated with its own design, and be adjustable to match frequency dependent losses expected from printed circuit boards (PCBs), radio frequency (RF) cables, and other circuitry. Conventional ISI filter architecture relies on the general concept that internal parasitic losses in the design must be compensated for using additional amplified signal, leading to designs requiring very high power. This architecture is based on the idea that parasitic losses should be hidden, or bypassed, when high bandwidth operation is needed. Accordingly, there is a need for low power ISI filters.